The present invention relates to the field of instruction controlled digital computers and specifically to methods and apparatus associated with virtual and real addressing in data processing systems.
It is common in data processing systems to have a memory hierarchy wherein buffer memories of relatively low capacity, but of relatively high speed, operate in cooperation with main memories of relatively high capacity but of relatively low speed. It is desired that the vast majority of accesses, either to fetch or store information, be from the buffer memory so that the overall access time of the system is enhanced. In order to have the vast majority of accesses come from the relatively fast buffer memory, information is exchanged between the main memory and the buffer memory in accordance with predetermined algorithms.
The efficiency with which a buffer memory works in decreasing the access time of the overall system is dependent on a number of variables. For example, the variables include the capacity of the buffer memory, the capacity of the main store, the data transfer rate between stores, the replacement algorithms which determine when transfers between the main store and buffer are made, and the virtual-to-real address translation methods and apparatus.
In recent data processing systems, the addressing of storage units has been carried out using logical addresses. Logical addresses are typically defined to be either virtual addresses or real addresses. Both the real addresses and the virtual addresses must be transformed in order to actually address a physical address location in memory. The physical address location in memory is frequently called a system address. However, even system addresses may require one or more transforms to arrive at final physical addresses. Therefore, before a system address location can be accessed using a logical address, the logical address must be transformed to the system address. If the logical address is a virtual address, then the transform is a virtual-to-system transform. If the logical address is a real address, then the transform is a real-to-system transform. In some systems, a virtual-to-system transform can be implemented in steps with a virtual-to-real transform followed by a real-to-system transform. In some systems, real addresses are equivalent to system addresses, making the real-to-system transform trivial.
The transforms employed for real addresses are typically less complex than the transforms for virtual addresses. Usually, the real-to-system transforms include prefixing and/or base adjustment. The virtual-to-system address transforms however, generally employs a table in mainstore which specifies the transform.
Each virtual address space typically has a virtual address space descriptor which identifies the transform tables which are to be utilized in transforming the virtual address to a system address.
The transformation process for transforming logical addresses to system addresses is time consuming process, particularly for virtual addresses which typically have translation tables stored in main store.
In order to speed up the translation process, translation lookaside buffers have been employed. In such translation buffers, the translation information resulting from a translation of a logical address to a system address are saved once the translation has been made. When an access to the same location is desired and the translation information is already stored in the translation buffer, time is saved since the re-translation from the logical address to the system address is not required to be made.
In many data processing systems, for a significant portion of the address space, the virtual-to-system transform and the real-to-system transform are identical, that is, numerically equivalent virtual and real addresses are transformed to the same system address.
In prior art systems, in spite of this identity, both virtual-to-system and real-to-system transforms have been carried out and independently placed in the translation lookaside buffer. This process of storing both transforms in the TLB is wasteful of system resources.
In view of the background, there is a need to be less wasteful of system resources and to provide mechanisms which take advantage of the identity of the transforms.
In view of the above background, there is a need for new and improved mechanisms which are particularly useful in systems using virtual addressing.